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HI-6010
January 2006
ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS FEATURES
! ! ! ! ! ! ! ARINC 429 protocol controller with interface to an 8 bit bus Automatic label recognition option 8 bit or 32 bit buffering option Self test and parity options CMOS / TTL logic pins Plastic and ceramic package options - surface mount or DIP Military processing available
GENERAL DESCRIPTION
The HI-6010 is a CMOS integrated circuit designed to interface the avionics data bus standard ARINC 429 to an 8 bit port. It contains one receiver and one transmitter. They operate independently except for the self test option and the parity option. The receiver demands that the incoming data meet the standard protocol and the transmitter outputs a standard protocol stream. The HI-6010 provides flexible options for interfacing to the user system. The controlling processor can operate both the receiver and transmitter either by using hard wired flags and gates at the pins or by using software reads and writes of the Status Register and Control Register or a combination thereof. The chip is programmable to operate with single 8 bit bytes requiring "on the fly transmitter loading and receiver downloading" or to operate in 32 bit "extended buffer" mode. In addition there is an option to use automatic label recognition after loading 8 possible labels for comparison. Parity and self test are also software programmable. Master Reset is activated only by taking the MR pin high. Two clock inputs allow independent selection of the data rates of the transmitter and receiver. Each must be 4X the desired ARINC 429 frequency. Error flags are generated for transmitter underwrites and for receiver data framing miscues, parity errors, and buffer overwrites. The HI-6010 is a 5 volt chip that will require data translation from and to the ARINC bus. The HI-8482 and HI-8588 line receivers are available for the receiver side and the HI-318X and HI-858X line drivers are available for the transmitter side.
PIN CONFIGURATION (Top View)
VSS WEF CTS TXC HFS MR TXE RXRDY TXRDY TXD0 TXD1 RXC FCR RXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RE C/D CS WE D7 D6 D5 D4 D3 D2 D1 D0 RXD1 VDD
Pin numbers apply for plastic and ceramic DIP and for plastic PLCC. Consult factory for pin out of 48 lead ceramic leadless chip carrier.
APPLICATIONS
! Avionics Data Communication ! Serial to Parallel Conversion ! Parallel to Serial Conversion
OPERATING SUPPLY VOLTAGE
! VDD = 5.0 VOLTS 5% ! VSS = 0.0 VOLTS
(DS6010 Rev.D)
HOLT INTEGRATED CIRCUITS www.holtic.com
01/06
HI-6010
PIN DESCRIPTIONS
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SYMBOL
VSS WEF CTS TXC HFS MR TXE RXRDY TXRDY TXD0 TXD1 RXC FCR RXD0 VDD RXD1 D0 D1 D2 D3 D4 D5 D6 D7 WE CS C/D RE
FUNCTION
POWER OUTPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT INPUT POWER INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT INPUT 0.0 Volts
DESCRIPTION
Error indication if high. Status register must be read to determine specific error. Enables data transmission when low. Source clock for data transmission. 4 times bit rate. Hardware feature select. Master reset, active high. Low when transmission in progress. High when data of received word is available. High when data of a transmitted word may be input. "Zeroes" data output of transmitter. "Ones" data output of transmitter. Source clock for data reception. 4 times bit rate. First character received flag. "Zeroes" data input to receiver. 5 Volts 5% "Ones" data input to receiver. Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus 8 bit data bus input control active low. Chip select, active low. High for control or status register operations, low for data 8 bit data bus output control, active low.
USING THE RECEIVER
The receiver logic is independent of the transmitter except in the following ways: 1. Self Test 2. Parity Option In self test, the transmitter outputs route to the receiver inputs internally ignoring the external inputs. Also in self test, the external receiver clock is replaced with the transmitter clock. The parity option affects both the receiver and transmitter. Either both are operational or neither.
goes high for any one of three receiver errors. The status register will show which of the three errors occurred: Status Register Bit SR3 SR4 SR5 Error Received a parity error Data Overwritten Receiving sequence error
The possible Receiver sequence errors are: 1. RXD0 and RXD1 simultaneously a one. 2. Less than 32 bits before 3 nulls. 3. More than 32 bits. There are no errors flagged for labels received that don't match stored labels when in the label recognition mode. Errors are cleared by MR or by reading the Status Register.
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
WEF is an error indicator. It goes high for a transmitter "underwrite" (failure to keep up with byte loading) and pin 2
PIN 5 - HFS and the CONTROL REGISTER
This pin, along with the control register, sets up the functioning (e.g. modes) of the chip. If HFS is low, the
HOLT INTEGRATED CIRCUITS 2
HI-6010
USING THE RECEIVER (cont.)
receiver is not programmable to the 32 bit "extended buffer" mode nor to the label recognition mode. Affecting the receiver:
PIN 14 - RXD0 and PIN 16 - RXD1
These pins must be 5 volt logic levels. There must be a translator between the ARINC bus and these inputs. Typically a receiver chip, such as the HI-8482 or HI-8588 is inserted between the ARINC bus and the logic chips. RXD0 is looking for a high level for zero inputs and RXD1 is looking for a high level for one inputs. When both inputs are low this is referred to as the Null state.
CONTROL PROGRAM PIN 5 BIT NAME VALUE VALUE
OPERATION
CR1
X 0 1
0 1 1
No action No action Next 8 data read cycles will read stored labels. One time only sequence on each transiton of CR1 to a 1. Receiver is disabled Receiver is enabled RXRDY goes high normally Blocks RXRDY for one ARINC word Self test disabled Self test enabled No parity errors enabled and 32nd bit is data Parity error flag enabled 32 bit "extended mode" enabled and parity enabled. 8 bit "one byte at a time" mode and parity enabled. Label recognition not programmable Label recognition disabled Label recognition enabled
SOFTWARE CONTROL OF THE RECEIVER
By writing to the Control Register and reading the Status Register the controlling processor can operate the receiver without hardware interrupts. The Control Register in combination with the wiring of pin 5 was explained above. The Status Register bits pertaining to the receiver are explained below:
STATUS BIT VALUE MEANING
CR2 CR3* CR4 CR5
0 1 0 1 0 1 0 1 0 1
X X X X X X 0 0 1 1 0 1 1
SR1 SR3 SR4 SR5
0 1 0 1 0 1 0 1 0 1
No receiver data Receiver data ready No parity error Parity error - Parity was even Receiver data not overwritten Receiver data was overwritten Receiver data received without framing error Framing error - Did not receive exactly 32 good bits Did not receive first byte Received first byte - Same flag as pin 13
CR7
X 0 1
SR6
* CR3 will be automatically reset to 0 after being programmed to a 1 at the completion of an ARINC word reception. This allows a software label recognition different from the automatic option available.
COMMUNICATING WITH THE CONTROL AND STATUS REGISTERS
Pin 27, C/D, must be high to read the status register or write the control register. Reading the status register resets errors. There is no provision to read the control register.
PIN 6 - MR
When MR is a 1, the control word is set to 0X10 0101 (CR7 CR0). For the receiver this sets up 8 bit mode with the receiver and parity enabled. MR also initializes the registers and logic. The first ARINC reception will only occur after a word gap.
PIN 8 - RXRDY
LABEL RECOGNITION OPTION
Pin 5 must be high if label recognition is selected in either the 8 or 32 bit modes and all eight label buffers must be written using redundant labels, if necessary. The chip compares the incoming label to the stored labels. If a match is found, the data is processed. If a match is not found, no indicators of receiving ARINC data are presented.
In 8 bit mode, this pin goes high whenever 8 bits are received without error. In 32 bit mode, this pin goes high after all 32 bits are received with no error. This flag may be inhibited for one ARINC word if CR3 is programmed to 1. This flag is also inhibited in label recognition if the incoming ARINC label does not match one of the stored 8 labels.
LOADING LABELS
After the write that changes CR7 from 0 to 1, the next 8 writes of data (C/D is a zero for data) will load the label registers. Labels must be loaded whenever pin 5 goes from low to high.
PIN 12 - RXC
This pin must have a clock applied that is 4X the desired receive frequency.
PIN 13 - FCR
In 8 bit mode, this pin flags the first character (byte) received. In 32 bit mode, this pin goes high for a valid 32 bit word. The pin is not affected by CR3 programming.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 8 data reads are labels.
HOLT INTEGRATED CIRCUITS 3
HI-6010
USING THE TRANSMITTER
The transmitter logic is independent of the receiver except in the following ways: 1. Self Test 2. Parity Option In self test the transmitter outputs route to the receiver inputs internally and the TXD0 and TXD1 outputs are inhibited. When parity is enabled, both the receiver and transmitter are affected. Odd parity is automatically generated in the 32nd bit if this option is selected.
PIN 7 - TXE
Whenever a transmission begins, this pin goes low and returns high after the transmission is complete.
PIN 9 - TXRDY
Whenever TXRDY is a one, data may be written into the transmitter buffer. In 8 bit "one byte at a time" mode, this pin may be monitored to indicate when to write the next 8 bits.
PIN 10 - TXD0 and PIN 11 - TXD1
TXD0 will go high during a transmission if the data is zero. TXD1 goes high if data is a one. When both pins are low this is referred to as the Null state. Typically an ARINC transmitter chip, such as the HI-3182, HI-3183, HI-8585 or HI-8586 is connected to these pins to translate the 5 volt levels to the proper ARINC bus levels. Data is not output when the HI-6010 is in self-test mode.
HARDWARE CONTROL OF THE TRANSMITTER
PIN 2 - WEF
This output goes high for 1 transmitter error and 3 receiver errors. To determine which error is being flagged, read the Status Register. Reading the Status Register also clears the error flag. The transmitter will not function until the error is cleared. It can also be cleared by MR going high. The only possible transmitter error is generated when running in 8 bit mode. For the transmitter this means loading the last 3 bytes while the transmission is in progress. Failure to load a byte before the previous byte's 8th bit is transmitted will generate the error, indicated by status bit SR7 set to a 1.
SOFTWARE CONTROL OF THE TRANSMITTER
By writing into the Control Register and reading the Status Register, the controlling processor can operate the transmitter independent of the flags at the pins. Transmission can be initiated by changing CR0 from a 0 to a 1 after the transmitter buffer has been loaded. Then the Status Register may be monitored as follows:
STATUS BIT SR0 SR2 SR7 VALUE 0 1 0 1 0 1 MEANING Do not load the transmitter buffer Ready to load the transmitter buffer Transmission in progress Transmitter is idle No transmission error 8 bit mode only error for underwriting data
PIN 3 - CTS
This pin is a hardware gate for transmissions. If the transmitter buffer is loaded and Control Register bit CR0 is a one, the only inhibit of the transmitter would be for CTS to be a one. When taken low, transmission of an ARINC word is enabled. It may be pulsed to release each transmitted word.
PIN 4 - TXC
The data rate of transmission is controlled by this pin. This clock must be 4X the desired date rate.
PIN 5 - HFS and the CONTROL REGISTER
This pin along with the Control Register sets the functioning of the chip. For the transmitter:
CONTROL BIT NAME PROGRAM VALUE PIN 5 VALUE
APPLICATIONS TIPS
Cabling Noise The HI-6010 has TTL compatible inputs and therefore they are susceptible to noise near ground. If the data bus is passed by ribbon cable or the equivalent to the device under test, it is possible to get significant glitches on the Master Reset line. The problem will appear to be a pattern sensitive failure. One cure is simply to adequately bypass Master Reset. Another is to buffer the HI-6010 inputs near the chip. Receiver Seems Dead After Master Reset the HI-6010 receiver must see a word gap before the first ARINC data bit. Error flags must be cleared by either a Status Register Read or by a Master Reset. The operation of either the transmitter or the receiver is inhibited upon error.
OPERATION Transmitter is disabled Transmitter is enabled Not in self test Self test enabled 8 bit mode + data in 32nd bit 8 bit mode + parity enabled 32 bit mode with parity enabled 8 bit mode with parity enabled
CR0 CR4 CR5
0 1 0 1 0 1 0 1
X X X X 0 0 1 1
PIN 6 - MR The chip is initialized whenever this pin goes high. The Control Register is set to 0X10 0101 (CR7 - CR0). For the transmitter this sets up 8 bit mode with the transmitter enabled.
HOLT INTEGRATED CIRCUITS 4
HI-6010
8 BIT "ONE BYTE AT A TIME" TRANSMIT USING TXRDY, PIN 9, TO TRIGGER NEXT BYTE LOAD
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0P
24 0
23 0
TD7
22 0*
TD6
21 0
TD5
20 0
TD4
19 0
TD3
18 0
TD2
17 1
TD1
MR
6 0 0 0
5
3
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
0 X 1 X 1 X Load Control Word 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 X TXRDY & TXE Go Low After Load Data 0 X 1 X Monitor Pin 9 to Go High 0 X 0 X After Pin 9 High Then Load Next Byte 0 X 1 X Monitor Pin 9 to Go High 0 X 0 X Load 0 X 1 X Monitor Pin 9 to Go High 0 X 0 X Load 1 X 1 X Transmission Complete
0 P TD8 0 1 X
X
X
X
X
X
X
X
0 P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9 0 0 1 X X X X X X X X 0
0 P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0 0 1 X X X X X X X X 0
0 P TD32 TD31 TD30 TD29 TD28 TD27 TD26 TD25 0 1 1 X X X X X X X X 0
* With Pin 5 low, Control Register Bit 5 selects if the 32nd bit is either odd parity or data. P = Pulse X = Don't Care
8 BIT "ONE BYTE AT A TIME" TRANSMIT MONITORING STATUS REGISTER BIT 0
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 0 0P
24 0
23 0
TD7
22 0*
TD6
21 0
TD5
20 0
TD4
19 0
TD3
18 0
TD2
17 1
TD1
MR
6 0 0 0 0
5 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0 0 0
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
1 X 1 X Load Control Word D0 = 1 0 X 0 X Load Data to Transmit - Byte 1 0 X 0 X Status Bits 0, 2 & 7 (TXRDY, TXE & ERROR) 0 X 1 X Status Bit 0 Goes High 0 X 0 X Load the Next Byte to Transmit 0 X 0 X Monitor Status Bit 0 0 X 1 X Detect a Transition 0 X 0 X Load 3rd Byte 0 X 0 X Monitor Status Bit 0 0 X 1 X Detect a Transition 0 X 0 X Load 4th Byte
0 P TD8 0 0 1 1 0 0
P1 P1 1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
P1 P1 1 0
0 P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
P1 P1 1 0
0 P TD32 TD31 TD30 TD29 TD28 TD27 TD26 TD25 0
* With Pin 5 low, Control Register Bit 5 selects if the 32nd bit is either odd parity or data. P = Pulse X = Don't Care
HOLT INTEGRATED CIRCUITS 5
HI-6010
RECEIVING 32 BIT WORDS HARDWARE INTERRUPT
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 0P 0 0 0 0 0 0 1
24 0 X
23 0 X
22 0 X
RD6
21 0 X
RD5
20 0 X
RD4
19 1 X
RD3
18 0 X
RD2
17 0 X
MR
6 0 0
5
3
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS Write CR: 32 Bit Recieve & No Label Recogn. Await Pin 8 or Pin 13 to Go High Read 1st Byte Read 2nd Byte Read 3rd Byte Read 4th Byte
1XX0X0 1XX1X1 1XX1X1 1XX1X0 1XX1X0 1XX1X0 1XX0X0
P0 P0 P0 P0 1 0
1 RD8 RD7
RD1 0
1 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RD9 0 1 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 0 1 PAR RD31 RD30 RD29 RD28 RD27 RD26 RD25 0 1 X X X X X X X X 0
P = Pulse X = Don't Care
RECEIVING 8 BIT MODE SOFTWARE INTERRUPT
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 0P 0 0 0 0 0 0 0 0 0 0 0 0 1 1
24 0 0 0
23 0 0 1
22 1 0 0
RD6
21 0 0 0
RD5
20 0 0 0
RD4
19 1 X X
RD3
18 0 0 1
RD2
17 0 0 0
MR
6 0 0 0
5
3
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS Write CR: 8 Bit Receive & Not Label Recong. Monitor the Status Register SR 1 & SR 6 Go High - First Character Read 1st Byte Look for SR 1 to Go High Again
1XX0X0 1XX0X0 1XX1X1 1XX0X0 1XX0X0 1XX1X0 1XX0X0 1XX0X0 1XX1X0 1XX0X0 1XX0X0 1XX1X0 1XX0X0
P1 P1 P0 P1 P1 P0 P1 P1 P0 P1 P1 P0
1 RD8 RD7 1 1 0 0 0 0
RD1 0
0 0
0 0
0 0
X X
0 1
0 0
0 0
1 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RD9 0 1 1 0 0 0 0 0 0 0 0 0 0 X X 0 1 0 0 0 0
Read 2nd Byte Look for SR 1 to Go High Again
1 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 0 1 1 0 0 0 0 0 0 0 0 0 0 X X 0 1 0 0 0 0
Read 3rd Byte Look for SR 1 to Go High Again
1 PAR RD31 RD30 RD29 RD28 RD27 RD26 RD25 0
Read 4th Byte
P = Pulse X = Don't Care
HOLT INTEGRATED CIRCUITS 6
HI-6010
TRANSMIT IN 32 BIT MODE (EXTENDED BUFFER) USING CTS TO INITIATE
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 1 1 1 0 0 0 0 1 0P
24 0
23 0
TD7
22 0
TD6
21 0
TD5
20 0
TD4
19 0
TD3
18 0
TD2
17 1
TD1
MR
6 0 0
5 1 1 1 1 1 1
3 1 1 1 1 1 0
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
1 X 1 X Load Control Word D5 = 0 & D0 = 1 1 X 1 X Load Data to Transmit - Byte 1 1 X 1 X Load Data to Transmit - Byte 2 1 X 1 X Load Data to Transmit - Byte 3 1 X 0 X Load Data to Transmit - Byte 4 1 X 0 X Take CTS Low to Start Transmitting 32nd Bit Will Be Parity
0 P TD8
0 P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9 0 0 P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0 0P 1 1 X X TD31 TD30 TD29 TD28 TD27 TD26 TD25 0 X X X X X X X 0
P = Pulse X = Don't Care
TRANSMIT IN 32 BIT MODE (EXTENDED BUFFER) USING SOFTWARE WRITE TO CONTROL REGISTER
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 1 1 1 0 0 0 0 1 0P
24 0
23 0
TD7
22 0
TD6
21 0
TD5
20 0
TD4
19 0
TD3
18 0
TD2
17 0
TD1
MR
6 0 0
5 1 1 1 1 1 1
3 0 0 0 0 0 0
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
1 X 1 X Load Control Word D5 = 0 & D0 = 0 1 X 0 X Load Data to Transmit - Byte 1 1 X 0 X Load Data to Transmit - Byte 2 1 X 0 X Load Data to Transmit - Byte 3 1 X 0 X Load Data to Transmit - Byte 4 0 X 0 X Write Control Word D0 = 1 32nd Bit Will Be Parity
0 P TD8
0 P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9 0 0 P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0 0P 0P X 0 TD31 TD30 TD29 TD28 TD27 TD26 TD25 0 0 0 0 0 0 0 1 0
P = Pulse X = Don't Care
HOLT INTEGRATED CIRCUITS 7
HI-6010
LOADING LABELS
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0P 0P
24 0 1
23 0 0 1L6 2L6 3L6 4L6 5L6 6L6 7L6 8L6
22 0 0 1L5 2L5 3L5 4L5 5L5 6L5 7L5 8L5
21 0 0 1L4 2L4 3L4 4L4 5L4 6L4 7L4 8L4
20 0 0 1L3 2L3 3L3 4L3 5L3 6L3 7L3 8L3
19 1 1 1L2 2L2 3L2 4L2 5L2 6L2 7L2 8L2
18 0 0 1L1 2L1 3L1 4L1 5L1 6L1 7L1 8L1
17 0 0 1L0 2L0 3L0 4L0 5L0 6L0 7L0 8L0
MR
6 0 0 0 0 0 0 0 0 0 0
5
3
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
1 X X X X X Control Bit 7 Must Be 0 First 1 X X X X X Write 1 into Control Bit 7 1 X X X X X Load the 1st Label 1 X X X X X Load the 2nd Label 1 X X X X X Load the 3rd Label 1 X X X X X Load the 4th Label 1 X X X X X Load the 5th Label 1 X X X X X Load the 6th Label 1 X X X X X Load the 7th Label 1 X X X X X Load the 8th Label
0 P 1L7 0 P 2L7 0 P 3L7 0 P 4L7 0 P 5L7 0 P 6L7 0 P 7L7 0 P 8L7
P = Pulse X = Don't Care
READING LABELS
PINS
RXRDY
TXRDY
REC/D CS WE D7
D6
D5
D4
D3
D2
D1
D0
28 27 26 25 1 1 1 1 0P 0P 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
24 1 1 1L7 2L7 3L7 4L7 5L7 6L7 7L7 8L7
23 0 0 1L6 2L6 3L6 4L6 5L6 6L6 7L6 8L6
22 0 0 1L5 2L5 3L5 4L5 5L5 6L5 7L5 8L5
21 0 0 1L4 2L4 3L4 4L4 5L4 6L4 7L4 8L4
20 0 0 1L3 2L3 3L3 4L3 5L3 6L3 7L3 8L3
19 1 1 1L2 2L2 3L2 4L2 5L2 6L2 7L2 8L2
18 0 1 1L1 2L1 3L1 4L1 5L1 6L1 7L1 8L1
17 0 0 1L0 2L0 3L0 4L0 5L0 6L0 7L0 8L0
MR
6 0 0 0 0 0 0 0 0 0 0
5
3
7
8
9 13
FCR
HFS
CTS
TXE
COMMENTS
1 X X X X X Make Sure Bit 1 of Control Word is 0 1 X X X X X Write 1 into Control Bit 1 1 X X X X X Read the 1st Label 1 X X X X X Read the 2nd Label 1 X X X X X Read the 3rd Label 1 X X X X X Read the 4th Label 1 X X X X X Read the 5th Label 1 X X X X X Read the 6th Label 1 X X X X X Read the 7th Label 1 X X X X X Read the 8th Label
P0 P0 P0 P0 P0 P0 P0 P0
P = Pulse X = Don't Care
HOLT INTEGRATED CIRCUITS 8
HI-6010
TIMING DIAGRAMS
DATA BUS TIMING - READ
C/D
VALID
DATA BUS TIMING - WRITE
C/D
VALID
tCDS
RD
tCDH
WE
tCDS
tWP
tCDH
tRD tDR
DATA BUS
VALID
tDWS tDWH
DATA BUS
VALID
tCSSR
CS
tCSHR
CS
tCSSW
tCSHW
Figure 1.
Figure 2.
TRANSMTTER OPERATION
CTS
RECEIVER OPERATION
tCTL
TXE
tCPW tDTX
FIRST BIT LAST BIT
tENDAT
TXD0/ TXD1 TXRDY
tTXRY
RXD0/ RXD1 RXRDY/ FCR
LAST BIT
tDR
Figure 3.
Figure 4.
HOLT INTEGRATED CIRCUITS 9
HI-6010
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VSS = 0V) Supply Voltage: Input Voltage Range Input Current Output Current VDD VIN IIN -0.5V to +7.0V -0.5V to VDD +0.5V +10mA +25mA Power Dissipation Operating Temperature Range: Storage Temperature Range: Lead Temperature PD 500mW TA (Industrial) -40C to +85C TA (Hi temp & Military) -55C to +125C TSTG TLEAD -65C to +150C 300C for 60 Seconds
IOUT
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage Min. Input Voltage Max. Input Voltage Min. Input Current Max. Input Current Min. Output Voltage Max. Output Voltage (HI) (LO) (HI) (LO) (HI) (LO)
SYMBOL
VDD VIH VIL IIH IIL VOH VOL IDD CIN
CONDITION
MIN
4.75 2.1
TYP
5 1.4 1.4
MAX
5.25
UNITS
V V
0.7 1.5
V A A V
VIH = 4.9V VIL = 0.1V IOUT = -1.5mA IOUT = 1.8mA f = 400KHz Not tested 0.8 -1.5 2.7
0.7 2.8 20
V mA pF
Operating Current Drain Input Capacitance
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
DATA BUS TIMING - READ Setup C/D to RD Hold C/D to RD Delay RD to Data Delay Data Bus Hi-Z from RD Setup CS to RD Hold RD to CS DATA BUS TIMING - WRITE Set C/D to WE Hold C/D to WE Setup Data Bus to WE Hold Data Bus to WE Setup CS to WE Hold CS to WE Pulse Width WE TRANSMITTER TIMING Delay TXE from CTS Delay TXRDn from CTS Delay TXRDY from last TXDn Delay TXE from last TXDn CTS pulse width RECEIVER TIMING Delay Last RXDn to RXRDY MR pulse width (See Figure 4.) (See Figure 3.) (See Figure 2.) (See Figure 1.)
SYMBOL tCDS tCDH tRD tDR tCSSR tCSHR tCDS tCDH tDWS tDWH tCSSW tCSHW tWP tCTL tENDAT tTXRDY tTDTX tCPW tDR tMR
MIN
50 0
TYP
MAX
UNITS
ns ns
200 150 0 0 0 0 200 100 0 0 200 1.5 1 16 4 1 3 1 2.0
ns ns ns ns ns ns ns ns ns ns ns CLKS CLK CLKS DATA BITS CLK CLKS CLK
HOLT INTEGRATED CIRCUITS 10
HI-6010 ORDERING INFORMATION HI - 6010C x-xx
PART NUMBER TEMPERATURE RANGE FLOW BURN IN LEAD FINISH
Blank T M-01
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
Gold Gold Tin / Lead (Sn / Pb) Solder
C
28 PIN CERAMIC SIDE BRAZED DIP
HI - 6010J x x
PART NUMBER LEAD FINISH
Blank F
PART NUMBER
Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE RANGE FLOW BURN IN
Blank T
PART NUMBER
-40C TO +85C -55C TO +125C
PACKAGE DESCRIPTION
I T
NO NO
J
28 PIN PLASTIC J-LEAD PLCC
HOLT INTEGRATED CIRCUITS 11
HI-6010 PACKAGE DIMENSIONS
inches (millimeters)
28-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 28C
1.400 .014 (35.560 .356)
.610 .010 (15.494 .254)
.595 .010 (15.113 .254)
.200 MAX. (5.080 MAX.)
.050 TYP. (1.270 TYP.)
.085 .009 (2.159 .229)
.600 .010 (15.240 .254)
.125 MIN. (3.175 MIN.) .018 .002 (.457 .051) .100 .005 (2.540 .127)
010 +.002/-.001 (.254+.051/-.025)
28-PIN PLASTIC PLCC
Package Type: 28J
PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45 .050 .005 (1.27 .127) .031 .005 (.787 .127)
.490 .005 (12.446 .127) SQ.
.453 .003 (11.506 .076) SQ.
.017 .004 (.432 .102) SEE DETAIL A
.009 .011
.173 .008 (4.394 .203) DETAIL A .410 .020 (10.414 .508)
.015 .002 (.381 .051) .020 MIN (.508 MIN ) R .025 .045
HOLT INTEGRATED CIRCUITS 12

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